Datasheet

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 508 of 982
REJ09B0054-0600
14.3.10 IEBus Reception Master Address Register 1 (IEMA1)
IEMA1 indicates the lower four bits of the communications destination master unit address in
slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the
contents are changed at the timing of setting the RxS flag in IERSR.
If a broadcast receive error interrupt is selected by the DEE bit in IECTR and the receive buffer is
not in the receive enabled state on control field reception, a receive error interrupt is generated and
the lower 4 bits of the master address are stored in IEMA1. This register cannot be modified.
Bit Bit Name Initial Value R/W Description
7
6
5
4
IMA3
IMA2
IMA1
IMA0
0
0
0
0
R
R
R
R
Lower 4 Bits of IEBus Reception Master Address
Indicate the lower 4 bits of the communications
destination master unit address in slave/broadcast
reception.
3 to 0 ⎯ All 0 R Reserved
These bits are always read as 0.
14.3.11 IEBus Reception Master Address Register 2 (IEMA2)
IEMA2 indicates the upper 8 bits of the communications destination master unit address in
slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the
contents are changed at the timing of setting the RxS flag in IERSR.
If a broadcast receive error interrupt is selected with the DEE bit in IECTR and the receive buffer
is not in the receive enabled state at control field reception, a receive error interrupt is generated
and the upper 8 bits of the master address are stored in IEMA2. This register cannot be modified
by a write.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
IMA11
IMA10
IMA9
IMA8
IMA7
IMA6
IMA5
IMA4
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Upper 8 Bits of IEBus Reception Master Address
Indicate the upper 8 bits of the communications
destination master unit address in slave/broadcast
reception.