Datasheet

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 6.00 Mar. 18, 2010 Page 492 of 982

REJ09B0054-0600

⎯ When bit 3 in the control bits is 1 (data write) although the slave receive buffer* is not

empty

⎯ When the control bits are set to the data read (H'3, H'7) although the slave transmit buffer*

is empty

⎯ When another unit which locked the slave unit requests H'3, H'6, H'7, H'A, H'B, H'E, or

H'F in the control bits although the slave unit has been locked

⎯ When the control bits are the locked address read (H'4, H'5) although the unit is not locked

⎯ When a timing error occurs

⎯ When the control bits are undefined

Note: * See section 14.1.3 (1), Slave Status Read (Control Bits: H'0, H'6).

The acknowledge bit at the end of the message length field becomes NAK in the following

cases and transfer is stopped.

⎯ When the parity of the message length bits is incorrect

⎯ When a timing error occurs

(d) Acknowledge Bit at the End of the Data Field

The acknowledge bit at the end of the data field becomes NAK in the following cases and

transfer is stopped.

⎯ When the parity of the data bits is incorrect*

⎯ When a timing error occurs after the previous transfer of the acknowledge bit

⎯ When the receive buffer becomes full and cannot accept further data

Note: * In this case, data field is transferred repeatedly until the number of data reaches the

maximum number of transfer bytes if the number of data does not exceed the

maximum number of transfer bytes in one frame.