Datasheet

Section 13 Watchdog Timer (WDT)
Rev. 6.00 Mar. 18, 2010 Page 468 of 982
REJ09B0054-0600
13.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
TCSR is cleared to 0.
To initialize TCNT to H'00 while the timer is operating, write H'00 to TCNT directly. See 13.6.7,
Notes on Initializing TCNT by Using the TME Bit.
13.3.2 Timer Control/Status Register (TCSR)
TCSR functions include selecting the clock source to be input to TCNT and the timer mode.
• TCSR_0
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W)
*
1
Overflow Flag
Indicates that TCNT has overflowed. Only a 0 can
be written to this bit, to clear the flag.
[Setting condition]
When TCNT overflows (changes from H'FF to
H'00)
When internal reset request generation is selected
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
Cleared by reading TCSR*
2
when OVF = 1, then
writing 0 to OVF
6 WT/IT 0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode (an interval timer interrupt
(WOVI) is requested to CPU)
1: Watchdog timer mode (internal reset selectable)
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and
is initialized to H'00.
4, 3 ⎯ All 1 ⎯ Reserved
These bits are always read as 1 and cannot be
modified.