Datasheet

Section 13 Watchdog Timer (WDT)
Rev. 6.00 Mar. 18, 2010 Page 466 of 982
REJ09B0054-0600
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal reset signal*
1
Reset
control
RSTCSR TCNT_0 TCSR_0
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
Clock
select
Internal clock
sources
Bus
interface
Module bus
TCSR_0:
TCNT_0:
RSTCSR:
Notes: 1. The type of internal reset signal depends on a register setting.
The power-on reset or manual reset can be selected as the internal reset.
2. When a sub-clock is operating in power-down mode, φ will be φ
SUB
.
Timer control/status register0
Timer counter0
Reset control/status register
WDT
Legend:
Internal bus
*
2
Figure 13.1 Block Diagram of WDT_0 (1)