Datasheet

Section 12 8-Bit Timers
Rev. 6.00 Mar. 18, 2010 Page 463 of 982
REJ09B0054-0600
No.
Timing of Switchover by Means of
CKS1 and CKS0 Bits
TCNT Clock Operation
3 Switching from high to low
*
3
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
CKS bit rewrite
NN + 1 N + 2
*
4
4 Switching from high to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
CKS bit rewrite
NN + 1N + 2
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
12.8.6 Contention between Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be
disabled before entering module stop mode.
12.8.7 Mode Setting of Cascaded Connection
When the 16-bit count mode and the compare-match count mode are set at the same time, input
clocks for TCNT_0 and TCNT_1 (TCNT_2 and TCNT_3)
*
are not generated and the timer stops
incrementation. This setting is prohibited.
Note: * Not available in the H8S/2237 Group and H8S/2227 Group.