Datasheet

Section 12 8-Bit Timers
Rev. 6.00 Mar. 18, 2010 Page 456 of 982
REJ09B0054-0600
12.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.8 shows the timing of this operation.
φ
Clear signal
External reset
input pin
TCNT N H'00N − 1
Figure 12.8 Timing of Clearing by External Reset Input
12.5.6 Timing of Overflow Flag (OVF) Setting
OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
12.9 shows the timing of this operation.
φ
OVF
Overflow signal
TCNT H'FF H'00
Figure 12.9 Timing of OVF Setting