Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 438 of 982
REJ09B0054-0600
11.10.9 Contention between TGR Write and Input Capture
If the input capture signal is generated in the T
2
state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 11.51 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
TGR write cycle
T
1
T
2
M
TGR
M
TGR address
Figure 11.51 Contention between TGR Write and Input Capture
11.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T
2
state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.52 shows the timing in this case.