Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 434 of 982
REJ09B0054-0600
Overlap
Phase
diffe-
rence
Phase
diffe-
rence
Overlap
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width Pulse width
Pulse width Pulse width
Notes: Phase difference and overlap:
Pulse width:
1.5 states or more
2.5 states or more
Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
11.10.3 Caution on Cycle Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
f =
φ
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
11.10.4 Contention between TCNT Write and Clear Operations
If the counter clearing signal is generated in the T
2
state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed. Figure 11.46 shows the timing in this
case.