Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 410 of 982
REJ09B0054-0600
Example of Cascaded Operation Setting Procedure: Figure 11.18 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
Start count
<Cascaded operation>
Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
[1]
[2]
[1]
[2]
Figure 11.18 Cascaded Operation Setting Procedure
Examples of Cascaded Operation: Figure 11.19 illustrates the operation when counting upon
TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been
designated as input capture registers, and the TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
TCNT_2
clock
TCNT_2 H'FFFF H'0000 H'0001
TIOCA1,
TIOCA2
TGRA_1 H'03A2
TGRA_2 H'0000
TCNT_1
clock
TCNT_1 H'03A1 H'03A2
Figure 11.19 Example of Cascaded Operation (1)
Figure 11.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.