Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 409 of 982
REJ09B0054-0600
TCNT value
H'09FB
H'0000
TGRC
Time
H'0532
TIOCA
TGRA
H'0F07H'0532
H'0F07
H'0532
H'0F07
H'09FB
Figure 11.17 Example of Buffer Operation (2)
11.4.4 Cascaded Operation
In cascaded operation*, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of
TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.29 shows the register combinations used in cascaded operation.
Notes:
When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.
* Not available in the H8S/2227 Group.
Table 11.29 Cascaded Combinations
Combination Upper 16 Bits Lower 16 Bits
Channels 1 and 2 TCNT_1 TCNT_2
Channels 4 and 5 TCNT_4 TCNT_5