Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 405 of 982
REJ09B0054-0600
For details on PWM modes, see section 11.4.5, PWM Modes.
TCNT0 to TCNT2 values
H'0000
TIOCA0
TIOCA1
TGRB_0
Synchronous clearing by TGRB_0 compare match
TGRA_2
TGRA_1
TGRB_2
TGRA_0
TGRB_1
TIOCA2
Time
Figure 11.12 Example of Synchronous Operation
11.4.3 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 11.28 shows the register combinations used in buffer operation.
Table 11.28 Register Combinations in Buffer Operation
Channel Timer General Register Buffer Register
0 TGRA_0 TGRC_0
TGRB_0 TGRD_0
3
*
TGRA_3 TGRC_3
TGRB_3 TGRD_3
Note: * Not available in the H8S/2227 Group.