Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 393 of 982
REJ09B0054-0600
11.3.5 Timer Status Register (TSR)
The TSR registers indicate the status of each channel. The TPU of the H8S/2227 Group has a total
of three TSR registers, one each for channels 0 to 2. In other groups, the TPU has a total of six
TSR registers, one each for channels 0 to 5.
Bit Bit Name Initial value R/W Description
7 TCFD 1 R Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4
*
3
, and 5
*
3
.
In channels 0 and 3
*
3
, bit 7 is reserved. It is always
read as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6 — 1 — Reserved
This bit is always read as 1 and cannot be
modified.
5 TCFU 0 R/(W)
*
1
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1, 2, 4
*
3
, and 5
*
3
are set
to phase counting mode.
In channels 0 and 3
*
3
, bit 5 is reserved. It is always
read as 0 and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4 TCFV 0 R/(W)
*
1
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred.
[Setting condition]
When the TCNT value overflows (changes from
H'FFFF to H'0000)
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1