Datasheet

Section 10 I/O Ports
Rev. 6.00 Mar. 18, 2010 Page 354 of 982
REJ09B0054-0600
• PF0/BREQ/IRQ2
The pin functions are switched as shown below according to the combination of operating
mode, the BRLE bit, and the PF0DDR bit.
Operating mode Modes 4 to 6 Mode 7
BRLE 0 1 ⎯
PF0DDR 0 1 ⎯ 0 1
Pin functions PF0 input pin PF0 output
pin
BREQ input
pin
PF0 input pin PF0 output
pin
IRQ2 input pin
*
Note: * When this pin is used as an external interrupt pin, do not specify other functions.
10.12 Port G
Port G is a 5-bit I/O port and has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
10.12.1 Port G Data Direction Register (PGDDR)
PGDDR specifies input or output of the port G pins using the individual bits. PGDDR cannot be
read; if it is, an undefined value will be read. This register is a write-only register, and cannot be
written by bit manipulation instruction. For details, see section 2.9.4, Access Methods for
Registers with Write-Only Bits.
Bit Bit Name
Initial
Value R/W Description
7 to
5
⎯ Undefined ⎯ Reserved
These bits are always read as undefined value.
4 PG4DDR 0/1
*
W
3 PG3DDR 0 W
2 PG2DDR 0 W
1 PG1DDR 0 W
When a pin is specified as a general purpose I/O port,
setting this bit to 1 makes the corresponding port G
pin an output port. Clearing this bit to 0 makes the pin
an input port.
0 PG0DDR 0 W
Note: * In modes 4 and 5, initial value is 1. In modes 6 and 7, initial value is 0.