Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 6.00 Mar. 18, 2010 Page 295 of 982
REJ09B0054-0600
Table 9.4 lists the register information in repeat mode. Figure 9.7 shows the memory mapping in
repeat mode.
Table 9.4 Register Information in Repeat Mode
Name Abbreviation Function
DTC source address register SAR Designates source address
DTC destination address register DAR Designates destination address
DTC transfer count register AH CRAH Holds number of transfers
DTC transfer count register AL CRAL Designates transfer count
DTC transfer count register B CRB Not used
SAR
or
DAR
DAR
or
SAR
Repeat area
Transfer
Figure 9.7 Memory Mapping in Repeat Mode
9.5.3 Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area.
The block size can be between 1 to 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been
completed, a CPU interrupt is requested.