Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 6.00 Mar. 18, 2010 Page 282 of 982
REJ09B0054-0600
Internal address bus
DTCERA
to
DTCERG
and DTCERI
Interrupt controller
Interrupt
request
DTC
On-chip
RAM
Internal data busCPU interrupt
request
MRA MRB
CRA CRB
DAR
SAR
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERG
and DTCERI:
DTVECR:
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to G and I
DTC vector register
Legend:
DTC service request
Control logic
Register information
DTVECR
Figure 9.1 Block Diagram of DTC
9.2 Register Descriptions
The DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU.
When activated, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to the RAM.