Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 246 of 982
REJ09B0054-0600
Figure 8.10 illustrates operation in single address mode (when sequential mode is specified).
Address T
Address B
Transfer
DAC
K
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + ( 1)
DTID
(2
DTSZ
(N 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 8.10 Operation in Single Address Mode (when Sequential Mode Is Specified)
Figure 8.11 shows an example of the setting procedure for single address mode (when sequential
mode is specified).