Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 245 of 982
REJ09B0054-0600
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCRH to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.
Table 8.8 summarizes register functions in single address mode.
Table 8.8 Register Functions in Single Address Mode
Function
Register DTDIR = 0 DTDIR = 1 Initial Setting Operation
23 0
MAR
Source
address
register
Destination
address
register
Start address of
transfer destination
or transfer source
See sections 8.5.2,
Sequential Mode,
8.5.3, Idle Mode, and
8.5.4, Repeat Mode.
DACK pin Write
strobe
Read
strobe
(Set automatically
by SAE bit; IOAR is
invalid)
Strobe for external
device
0
ETCR
15
Transfer counter Number of transfers See sections 8.5.2,
Sequential Mode,
8.5.3, Idle Mode, and
8.5.4, Repeat Mode.
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is
invalid; in its place the strobe for external devices (DACK) is output.