Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 242 of 982
REJ09B0054-0600
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
MAR = MAR – (–1)
DTID
· 2
DTSZ
· ETCRH
The same value should be set in ETCRH and ETCRL.
In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the
transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is
not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the
operation can be restarted from the transfer after that terminated when the DTE bit was cleared.
Figure 8.7 illustrates operation in repeat mode.
Address T
Address B
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + ( 1)
DTID
(2
DTSZ
(N 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 8.7 Operation in Repeat mode