Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 232 of 982
REJ09B0054-0600
Table 8.3 DMAC Activation Sources
Short Address Mode Full Address Mode
Activation Source
Channels
0A and 1A
Channels
0B and 1B
Normal
Mode
Block
Transfer
Mode
ADI O O × O
TXI0 O O × O
RXI0 O O × O
TXI1 O O × O
RXI1 O O × O
TGI0A O O × O
TGI1A O O × O
TGI2A O O × O
TGI3A O O × O
TGI4A O O × O
Internal
interrupts
TGI5A O O × O
DREQ pin falling edge input × O O O External
requests
DREQ pin low-level input × O O O
Auto-request × × O ×
Legend:
O: Can be specified
×: Cannot be specified
8.4.1 Activation by Internal Interrupt Request
An interrupt request selected as a DMAC activation source can also simultaneously generate an
interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt request, the DMAC accepts the interrupt request
independently of the interrupt controller. Consequently, interrupt controller priority settings are
irrelevant.
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a
DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA
transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared
unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highest-