Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 230 of 982
REJ09B0054-0600
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
DTC
IOAR_0A
ETCR_0A
IOAR_0B
ETCR_0B
IOAR_1A
ETCR_1A
IOAR_1B
ETCR_1B
DMATCR
DMACR_0B
DMACR_1B
DMAWER
DMACR_0A
DMACR_1A
DMABCR
Second transfer area
using chain transfer
First transfer area
MAR_0AH
MAR_0AL
MAR_0BH
MAR_0BL
MAR_1AH
MAR_1AL
MAR_1BH
MAR_1BL
Figure 8.2 Areas for Register Re-Setting by DTC (Channel 0A)
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.