Datasheet

Section 8 DMA Controller (DMAC)
Rev. 6.00 Mar. 18, 2010 Page 220 of 982
REJ09B0054-0600
• DMABCRL
Bit Bit Name Initial Value R/W Description
7
6
5
4
DTE1B
DTE1A
DTE0B
DTE0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Enable 1B
Data Transfer Enable 1A
Data Transfer Enable 0B
Data Transfer Enable 0A
If the DTE bit is cleared to 0 when DTIE = 1, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt
request to the CPU or DTC.
When DTE = 0, data transfer is disabled and
the DMAC ignores the activation source
selected by the DTF3 to DTF0 bits in DMACR.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation
source selected by the DTF3 to DTF0 bits in
DMACR. When a request is issued by the
activation source, DMA transfer is executed.
0: Data transfer is disabled
1: Data transfer is enabled
[Clearing conditions]
• When initialization is performed
• When the specified number of transfers
have been completed in a transfer mode
other than repeat mode
• When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE bit after reading
DTE = 0