Datasheet

Rev. 6.00 Mar. 18, 2010 Page xxvi of lx
REJ09B0054-0600
8.7.3 Medium-Speed Mode...........................................................................................277
8.7.4 Activation by Falling Edge on DREQ Pin ...........................................................278
8.7.5 Activation Source Acceptance.............................................................................278
8.7.6 Internal Interrupt after End of Transfer................................................................278
8.7.7 Channel Re-Setting..............................................................................................279
Section 9 Data Transfer Controller (DTC)........................................................281
9.1 Features.............................................................................................................................281
9.2 Register Descriptions........................................................................................................282
9.2.1 DTC Mode Register A (MRA) ............................................................................283
9.2.2 DTC Mode Register B (MRB).............................................................................284
9.2.3 DTC Source Address Register (SAR)..................................................................285
9.2.4 DTC Destination Address Register (DAR)..........................................................285
9.2.5 DTC Transfer Count Register A (CRA) ..............................................................285
9.2.6 DTC Transfer Count Register B (CRB)...............................................................285
9.2.7 DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI) ....286
9.2.8 DTC Vector Register (DTVECR)........................................................................287
9.3 Activation Sources............................................................................................................288
9.4 Location of Register Information and DTC Vector Table ................................................289
9.5 Operation ..........................................................................................................................293
9.5.1 Normal Mode.......................................................................................................294
9.5.2 Repeat Mode........................................................................................................294
9.5.3 Block Transfer Mode...........................................................................................295
9.5.4 Chain Transfer .....................................................................................................297
9.5.5 Interrupts..............................................................................................................298
9.5.6 Operation Timing.................................................................................................298
9.5.7 Number of DTC Execution States .......................................................................300
9.6 Procedures for Using DTC................................................................................................301
9.6.1 Activation by Interrupt.........................................................................................301
9.6.2 Activation by Software ........................................................................................301
9.7 Examples of Use of the DTC............................................................................................302
9.7.1 Normal Mode.......................................................................................................302
9.7.2 Software Activation .............................................................................................302
9.8 Usage Notes......................................................................................................................303
9.8.1 Module Stop Mode Setting ..................................................................................303
9.8.2 On-Chip RAM .....................................................................................................303
9.8.3 DTCE Bit Setting.................................................................................................303
Section 10 I/O Ports...........................................................................................305
10.1 Port 1.................................................................................................................................309