Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 193 of 982
REJ09B0054-0600
T
1
Address bus
φ
CS0
AS
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 7.19 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
T
1
CS0
AS
T
2
T
1
T
1
RD
Address bus
φ
Data bus
Full access Burst access
Only lower address changed
Read data Read data Read data
Figure 7.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)