Datasheet

Rev. 6.00 Mar. 18, 2010 Page xxiii of lx
REJ09B0054-0600
5.3 Register Descriptions........................................................................................................129
5.3.1 Interrupt Priority Registers A to L, and O (IPRA to IPRL, IPRO) ......................130
5.3.2 IRQ Enable Register (IER) ..................................................................................131
5.3.3 IRQ Sense Control Registers H and L (ISCRH and ISCRL)...............................131
5.3.4 IRQ Status Register (ISR)....................................................................................134
5.4 Interrupt Sources...............................................................................................................135
5.4.1 External Interrupts ...............................................................................................135
5.4.2 Internal Interrupts.................................................................................................136
5.4.3 Interrupt Exception Handling Vector Table.........................................................136
5.5 Operation...........................................................................................................................142
5.5.1 Interrupt Control Modes and Interrupt Operation................................................142
5.5.2 Interrupt Control Mode 0.....................................................................................145
5.5.3 Interrupt Control Mode 2.....................................................................................147
5.5.4 Interrupt Exception Handling Sequence ..............................................................148
5.5.5 Interrupt Response Times ....................................................................................150
5.5.6 DTC and DMAC Activation by Interrupt............................................................151
5.6 Usage Notes ......................................................................................................................154
5.6.1 Contention between Interrupt Generation and Disabling.....................................154
5.6.2 Instructions that Disable Interrupts......................................................................155
5.6.3 When Interrupts are Disabled ..............................................................................155
5.6.4 Interrupts during Execution of EEPMOV Instruction..........................................155
5.6.5 IRQ Interrupts Usage Notes.................................................................................156
5.6.6 NMI Interrupts Usage Notes................................................................................156
Section 6 PC Break Controller (PBC) .............................................................. 157
6.1 Features.............................................................................................................................157
6.2 Register Descriptions........................................................................................................158
6.2.1 Break Address Register A (BARA) .....................................................................158
6.2.2 Break Address Register B (BARB)......................................................................159
6.2.3 Break Control Register A (BCRA) ......................................................................159
6.2.4 Break Control Register B (BCRB).......................................................................160
6.3 Operation...........................................................................................................................160
6.3.1 PC Break Interrupt Due to Instruction Fetch .......................................................160
6.3.2 PC Break Interrupt Due to Data Access...............................................................161
6.3.3 Notes on PC Break Interrupt Handling................................................................161
6.3.4 Operation in Transitions to Power-Down Modes.................................................161
6.3.5 When Instruction Execution Is Delayed by One State.........................................162
6.4 Usage Notes ......................................................................................................................163
6.4.1 Module Stop Mode Setting ..................................................................................163
6.4.2 PC Break Interrupts..............................................................................................163