Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 186 of 982
REJ09B0054-0600
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Invalid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
D7 to D0
Valid
Write
Note: n = 7 to 0
High
High impedance
Figure 7.13 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
