Datasheet

Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 179 of 982
REJ09B0054-0600
7.5.1 On-Chip Memory (ROM, RAM) Access Timing
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 7.4 shows the on-chip memory access cycle. Figure 7.5 shows the
pin states.
T
1
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Figure 7.4 On-5Chip Memory Access Cycle
Bus cycle
T
1
UnchangedAddress bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High-impedance state
Figure 7.5 Pin States during On-Chip Memory Access