Datasheet

Section 6 PC Break Controller (PBC)
Rev. 6.00 Mar. 18, 2010 Page 159 of 982
REJ09B0054-0600
6.2.2 Break Address Register B (BARB)
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3 Break Control Register A (BCRA)
BCRA controls channel A PC breaks.
Bit Bit Name Initial Value R/W Description
7 CMFA 0 R/(W)
*
1
Condition Match Flag A
[Setting condition]
When a condition set for channel A is satisfied
[Clearing condition]
When 0 is written to CMFA after reading*
2
CMFA
= 1
6 CDA 0 R/W CPU Cycle/DTC Cycle Select A
Selects the channel A break condition bus master.
0: CPU
1: CPU, DTC, or DMAC
*
3
5
4
3
BAMRA2
BAMRA1
BAMRA0
0
0
0
R/W
R/W
R/W
Break Address Mask Register A2 to A0
These bits specify which bits of the break address
set in BARA are to be masked.
000: BAA23 to 0 (All bits are unmasked)
001: BAA23 to 1 (Lowest bit is masked)
010: BAA23 to 2 (Lower 2 bits are masked)
011: BAA23 to 3 (Lower 3 bits are masked)
100: BAA23 to 4 (Lower 4 bits are masked)
101: BAA23 to 8 (Lower 8 bits are masked)
110: BAA23 to 12 (Lower 12 bits are masked)
111: BAA23 to 16 (Lower 16 bits are masked)
2
1
CSELA1
CSELA0
0
0
R/W
R/W
Break Condition Select
Selects break condition of channel A.
00: Instruction fetch
01: Data read cycle
10: Data write cycle
11: Data read/write cycle