Datasheet

Section 6 PC Break Controller (PBC)
Rev. 6.00 Mar. 18, 2010 Page 158 of 982
REJ09B0054-0600
Output controlOutput control
Mask control
PC break
interrupt
Match signal
Mask control
BARA BCRA
BARB BCRB
Comparator
Control
logic
Comparator
Control
logic
Internal address
Access
status
Match signal
Figure 6.1 Block Diagram of PC Break Controller
6.2 Register Descriptions
The PC break controller has the following registers.
• Break address register A (BARA)
• Break address register B (BARB)
• Break control register A (BCRA)
• Break control register B (BCRB)
6.2.1 Break Address Register A (BARA)
BARA is a 32-bit readable/writable register that specifies the channel A break address.
Bit Bit Name Initial Value R/W Description
31 to 24 ⎯ Undefined ⎯ Reserved
These bits are read as an undefined value
and cannot be modified.
23 to 0 BAA23 to BAA0 All 0 R/W Break Address 23 to 0
These bits set the channel A PC break
address.