Datasheet

Section 5 Interrupt Controller
Rev. 6.00 Mar. 18, 2010 Page 134 of 982
REJ09B0054-0600
5.3.4 IRQ Status Register (ISR)
ISR indicates the status of IRQn (n = 7 to 0) interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R/W
*
R/W
*
R/W
*
R/W
*
R/W
*
R/W
*
R/W
*
R/W
*
IRQ7 to IRQ0 Flags
Indicates the status of IRQ7 to IRQ0 interrupt requests.
[Setting condition]
When the interrupt source selected by the ISCRH, or
ISCRL occurs
[Clearing conditions]
• Cleared by reading IRQnF flag when IRQnF = 1, then
writing 0 to IRQnF flag
• When interrupt exception handling is executed when
low-level detection is set and IRQn input is high level
• When IRQn interrupt exception handling is executed
when falling, rising, or both-edge detection is set
• When the DTC is activated by an IRQn interrupt, and
the DISEL bit in MRB of the DTC is cleared to 0
Note: * Only 0 can be written to this bit to clear the flag.