Datasheet

Section 4 Exception Handling
Rev. 6.00 Mar. 18, 2010 Page 119 of 982
REJ09B0054-0600
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exception
handling requests are accepted at all times in program execution state.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode set by the INTM1 and INTM0 bits in SYSCR.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the RES
or MRES pin, or when the watchdog timer overflows. The
CPU enters the power-on reset state when the RES pin is
low. The CPU enters the manual reset state when the
MRES pin is low.
Trace Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
Traces are enabled only in interrupt control mode 2. Trace
exception handling is not executed after execution of an
RTE instruction.
Interrupt Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
Low
Trap instruction
(TRAPA)
Started by execution of a trap instruction (TRAPA). Trap
instruction exception handling requests are accepted at all
times in program execution state.
4.2 Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses.