Datasheet

Rev. 6.00 Mar. 18, 2010 Page xi of lx
REJ09B0054-0600
Item Page Revision (See Manual for Details)
4.8 Usage Note
Figure 4.3 Operation When
SP Value Is Odd
126 Figure amended
SP H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFF
R1L
PC
SP
CCR
PC
SP
TRAPA instruction executed
SP set to H'FFFEFF
Data saved above SP
MOV.B R1L, @-ER7 executed
Contents of CCR lost
5.6.5 IRQ Interrupt 156 5.6.5 added
5.6.6 NMI Interrupts Usage
Notes
156 5.6.6 added
6.3.4 Operation in
Transitions to Power-Down
Modes
161 Description amended
• When the SLEEP instruction causes a transition from
high speed mode to subactive mode (figure 6.2 (B)).
7.6.4 Wait Control
(2) Pin Wait Insertion
191 Description amended
Setting the WAITE bit in BCRL to 1 enables wait insertion by
means of the WAIT pin.
9.2.5 DTC Transfer Count
Register A (CRA)
285 Description amended
In repeat mode or block transfer mode, the CRA is divided
into two parts; the upper 8 bits (CRAH) and the lower 8 bits
(CRAL). In repeat mode, CRAH holds the number of
transfers while CRAL functions as an 8-bit transfer counter
(1 to 256). In block transfer mode, CRAH holds the block
size while CRAL function as an 8-bit block size counter (1 to
256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the
count reaches H'00. This operation is repeated.
10.1.2 Port 1 Data Register
(P1DR)
310 Table amended
Bit Bit Name Initial Value R/W Description
7 P17DR 0 R/W
6 P16DR 0 R/W
5 P15DR 0 R/W
4 P14DR 0 R/W
3 P13DR 0 R/W
2 P12DR 0 R/W
1 P11DR 0 R/W
Output data for a pin is stored when the pin is
specified as a general purpose output port.
0 P10DR 0 R/W