Datasheet

Section 1 Overview
Rev. 6.00 Mar. 18, 2010 Page 51 of 982
REJ09B0054-0600
Pin No.
Type Symbol
TFP-100B
TFP-100BV
TFP-100G
TFP-100GV
FP-100B
FP-100BV
FP-100A
*
3
FP-100AV
*
3
BP-112
*
1
BP-112V
*
1
TBP-112A
*
4
TBP-112AV
*
4
I/O Function
Clock OSC2 57 60 H10 Input Connects to a 32.768 kHz crystal
resonator. See section 23, Clock Pulse
Generator, for typical connection diagrams
for a crystal resonator.
φ 68 71 D11 Output Supplies the system clock to external
devices.
Operating
mode
control
MD2
MD1
MD0
67
56
55
70
59
58
E9
H9
J11
Input Sets the operating mode. Inputs at these
pins should not be changed during
operation. Except for mode changing, be
sure to fix the levels of the mode pins
(MD2 to MD0) by pulling them down or
pulling them up until the power turns off.
System
control
RES
*
5
59 62 G8 Input Reset input pin. When this pin is low, the
chip enters the power-on reset state.
MRES 86 89 B7 Input When this pin is low, the chip enters the
manual reset state.
STBY
*
5
61 64 G11 Input When this pin is low, a transition is made
to hardware standby mode.
BREQ 75 78 C9 Input Used by an external bus master to request
the bus mastership to this LSI.
BACK 74 77 B11 Output Indicates that the bus mastership has
been granted to an external bus master.
FWE 66 69 E10 Input Enables/disables programming the flash
memory.
Interrupts NMI
*
5
60 63 G9 Input Nonmaskable interrupt pin. If this pin is not
used, it should be fixed high.
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
92
91
81
78
72
75
40
38
95
94
84
81
75
78
43
41
B5
A5
B8
B9
D9
C9
K6
J6
Input These pins request a maskable interrupt.