Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 956 of 982
REJ09B0054-0600
t
DACD1
T
1
T
2
t
DACD2
T
3
DACK1, DACK0
φ
AS
A23 to A0
RD
(read)
CS7 to CS0
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
Figure 27.21 DMAC Single Address Transfer Timing (Three-State Access)
