Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 943 of 982
REJ09B0054-0600
Condition A
Condition B Condition C
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
TMR Timer output delay
time
t
TMOD
⎯ 100 ⎯ 100 ⎯ 150 ns Figure
27.27
Timer reset input
setup time
t
TMRS
50 ⎯ 50 ⎯ 80 ⎯ ns Figure
27.29
Timer clock input
setup time
t
TMCS
50 ⎯ 50 ⎯ 80 ⎯ ns Figure
27.28
Timer
clock
Single
edge
t
TMCWH
1.5 ⎯ 1.5 ⎯ 1.5 ⎯ t
cyc
pulse
width
Both
edges
t
TMCWL
2.5 ⎯ 2.5 ⎯ 2.5 ⎯
WDT_1 BUZZ output delay
time
t
BUZD
⎯ 100 ⎯ 100 ⎯ 150 ns Figure
27.30
SCI
*
Asynchro-
nous
t
Scyc
4 ⎯ 4 ⎯ 4 ⎯ t
cyc
Figure
27.31
Input
clock
cycle
Synchro-
nous
6 ⎯ 6 ⎯ 6 ⎯
Input clock pulse
width
t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
Input clock rise
time
t
SCKr
⎯ 1.5 ⎯ 1.5 ⎯ 1.5 t
cyc
Input clock fall
time
t
SCKf
⎯ 1.5 ⎯ 1.5 ⎯ 1.5
Transmit data
delay time
t
TXD
⎯ 100 ⎯ 100 ⎯ 150 ns Figure
27.32
Receive data
setup time
(synchronous)
t
RXS
100 ⎯ 75 ⎯ 150 ⎯ ns
Receive data hold
time
(synchronous)
t
RXH
100 ⎯ 75 ⎯ 150 ⎯ ns
A/D
converter
Trigger input setup
time
t
TRGS
50 ⎯ 40 ⎯ 60 ⎯ ns Figure
27.33