Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 942 of 982
REJ09B0054-0600
(4) Timing of On-Chip Peripheral Modules
Table 27.56 lists the timing of on-chip peripheral modules.
Table 27.56 Timing of On-Chip Peripheral Modules
Condition A (ZTAT version): V
CC
= 2.7 V to 3.6 V, AV
CC
= 2.7 V to 3.6 V,
V
ref
= 2.7 V to AV
CC
, V
SS
= AV
SS
= 0 V,φ = 32.768 kHz,
2 to 10 MHz,T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition B (F-ZTAT version, masked ROM version):
V
CC
= 2.7 V to 3.6 V, AV
CC
= 2.7 V to 3.6 V,
V
ref
= 2.7 V to AV
CC
, V
SS
= AV
SS
= 0 V, φ = 32.768 kHz,
2 to 13.5MHz,T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition C (Masked ROM version): V
CC
= 2.2 V to 3.6 V, AV
CC
= 2.2 V to 3.6 V,
V
ref
= 2.2 V to AV
CC
, V
SS
= AV
SS
= 0 V, φ = 32.768 kHz,
2 to 6.25 MHz,T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition A
Condition B Condition C
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
I/O port Output data delay
time
t
PWD
⎯ 100 ⎯ 100 ⎯ 150 ns Figure
27.24
Input data setup
time
t
PRS
50 ⎯ 50 ⎯ 80 ⎯
Input data hold
time
t
PRH
50 ⎯ 50 ⎯ 80 ⎯
TPU Timer output delay
time
t
TOCD
⎯ 100 ⎯ 100 ⎯ 150 ns Figure
27.25
Timer input setup
time
t
TICS
50 ⎯ 40 ⎯ 60 ⎯
Timer clock input
setup time
t
TCKS
50 ⎯ 40 ⎯ 60 ⎯ ns Figure
27.26
Timer
clock
Single
edge
t
TCKWH
1.5 ⎯ 1.5 ⎯ 1.5 ⎯ t
cyc
pulse
width
Both
edges
t
TCKWL
2.5 ⎯ 2.5 ⎯ 2.5 ⎯