Datasheet

Section 26 Electrical Characteristics (H8S/2215T)
Page 798 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
26.4.4 Timing of On-Chip Supporting Modules
Table 26.7 lists the timing of on-chip supporting modules.
Table 26.7 Timing of On-Chip Supporting Modules
Conditions: V
CC
= PLLV
CC
= DrV
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
,
V
SS
= PLLV
SS
= DrV
SS
= AV
SS
= 0 V, φ = 16 MHz, 24 MHz, T
a
= –20°C to +75°C
(regular specifications), T
a
= –40°C to +85°C (wide-range specifications)
Item Symbol Min. Max. Unit Test Conditions
Output data delay time t
PWD
— 40 ns Figure 26.12 I/O port
Input data setup time t
PRS
30 —
Input data hold time t
PRH
30 —
TPU Timer output delay time t
TOCD
— 40 ns Figure 26.13
Timer input setup time t
TICS
30 —
Timer clock input setup time t
TCKS
30 — ns Figure 26.14
Single edge t
TCKWH
1.5 — t
cyc
Timer clock
pulse width
Both edges t
TCKWL
2.5 —
TMR Timer output delay time t
TMOD
— 41 ns Figure 26.15
Timer reset input setup time t
TMRS
29 — ns Figure 26.17
Timer clock input setup time t
TMCS
29 — ns Figure 26.16
TMR Single edge t
TMCWH
1.5 — t
cyc
Figure 26.16
Timer clock
pulse width
Both edges t
TMCWL
2.5 —
SCI Asynchronous t
Scyc
4 — t
cyc
Figure 26.18
Input clock
cycle
Synchronous 6 —
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5
Transmit data delay time t
TXD
— 40 ns Figure 26.19
Receive data setup time
(synchronous)
t
RXS
40 —
Receive data hold time
(synchronous)
t
RXH
40 —
A/D
converter
Trigger input setup time t
TRGS
30 — ns Figure 26.20