Datasheet

Section 24 Electrical Characteristics (H8S/2215)
REJ09B0140-0900 Rev. 9.00 Page 735 of 846
Sep 16, 2010
H8S/2215 Group
24.4.3 Bus Timing
Table 24.6 shows, Bus Timing.
Table 24.6 Bus Timing
Conditions: V
CC
= PLLV
CC
= DrV
CC
= 2.7 V to 3.6 V, AV
CC
= 2.7 V to 3.6 V, V
ref
= 2.7 V to AV
CC
,
V
SS
= PLLV
SS
= DrV
SS
= AV
SS
= 0 V, φ = 13 MHz to 16 MHz, T
a
= –20°C to +75°C
(regular specifications), T
a
= –40°C to +85°C (wide-range specifications)
Item Symbol Min. Max. Unit Test Conditions
Address delay time t
AD
— 50 ns
Address setup time t
AS
0.5 × t
cyc
– 30 — ns
Address hold time t
AH
0.5 × t
cyc
– 15 — ns
Figures 24.7, 24.8, 24.10
CS delay time t
CSD
— 50 ns Figures 24.7, 24.8
AS delay time t
ASD
— 50 ns Figures 24.7, 24.8, 24.10
RD delay time 1 t
RSD1
— 50 ns Figures 24.7, 24.8
RD delay time 2 t
RSD2
— 50 ns Figures 24.7, 24.8, 24.10
Read data setup time t
RDS
30 — ns
Read data hold time t
RDH
0 — ns
Read data access time 2 t
ACC2
— 1.5 × t
cyc
– 65 ns Figure 24.7
Read data access time 3 t
ACC3
— 2.0 × t
cyc
– 65 ns Figures 24.7, 24.10
Read data access time 4 t
ACC4
— 2.5 × t
cyc
– 65 ns Figure 24.8
Read data access time 5 t
ACC5
— 3.0 × t
cyc
– 65 ns
WR delay time 1 t
WRD1
— 50 ns
WR delay time 2 t
WRD2
— 50 ns Figures 24.7, 24.8
WR pulse width 1 t
WSW1
1.0 × t
cyc
– 30 — ns Figure 24.7
WR pulse width 2 t
WSW2
1.5 × t
cyc
– 30 — ns Figure 24.8
Write data delay time t
WDD
— 50 ns Figures 24.7, 24.8
Write data setup time t
WDS
0.5 × t
cyc
– 30 — ns Figure 24.8
Write data hold time t
WDH
0.5 × t
cyc
– 15 — ns Figures 24.7, 24.8
WAIT setup time t
WTS
50 — ns Figure 24.9
WAIT hold time t
WTH
10 — ns
BREQ setup time t
BRQS
50 — ns Figure 24.11
BACK delay time t
BACD
— 50 ns
Bus-floating time t
BZD
— 80 ns