Datasheet

Section 22 Power-Down Modes
Page 696 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
22.6 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the A/D converter are retained.
After reset clearance, all modules other than DTC and DMAC are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
When a transition is made to sleep mode with all modules stopped, the bus controller and I/O ports
also stop operating, enabling current dissipation to be further reduced.
22.7 φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 22.4 shows the state of the φ pin in each processing state.
Table 22.4 φ Pin State in Each Processing State
Register Settings
DDR PSTOP Normal Mode Sleep Mode
Software
Standby Mode
Hardware
Standby Mode
0 × High impedance High impedance High impedance High impedance
1 0 φ output φ output Fixed high High impedance
1 1 Fixed high Fixed high Fixed high High impedance
Legend:
×: Don’t care