Datasheet

Section 21 Clock Pulse Generator
Page 676 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
Table 21.6 shows the input conditions for the 48-MHz external clock.
Table 21.6 External Clock Input Conditions when Duty Adjustment Circuit Is Not Used
Item Symbol Min Max Unit Test Conditions
External clock frequency
(48 MHz)
t
FREQ
47.88 48.12 MHz
Clock rise time t
R48
— 5 ns
Clock fall time t
F48
— 5 ns
Figure 21.10
Duty (t
HIGH
/t
FREQ
) t
DUTY
40 60 %
t
HIGH
t
LOW
t
FREQ
t
R48
t
F48
V
CC
× 0.5
EXTAL48
90%
10%
Figure 21.9 48-MHz External Clock Input Timing
21.6.3 Pin Handling when 48-MHz External Clock Is Not Needed (On-chip PLL Circuit Is
Used)
When the 48-MHz external clock is not needed, connect the EXTAL48 pin to GND (Vss) and
leave the XTAL48 pin open as shown in figure 21.9.
EXTAL48
XTAL48
Open state
Figure 21.10 Pin Handling when 48-MHz External Clock Is Not Used