Datasheet

Section 21 Clock Pulse Generator
Page 674 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
and t
EXr
= t
EXf
= 6.25 ns, the maximum operating frequency becomes 13.3 MHz depending on the
clcok cycle time of 75 ns.
Table 21.5 External Clock Input Conditions when Duty Adjustment Circuit Is Not Used
VCC
= 2.7 V to 3.6 V
VCC
= 3.0 V to 3.6 V* Test
Item Symbol Min Max Min Max Unit Conditions
External clock input low
pulse width
t
EXL
31.25 — 20.8 — ns Figure 21.5
External clock input high
pulse width
t
EXH
31.25 — 20.8 — ns
External clock rise time t
EXr
— 6.25 — 5.25 ns
External clock fall time t
EXf
— 6.25 — 5.25 ns
Note: * Available only in H8S/2215R, H8S/2215T and H8S/2215C.
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 21.6 External Clock Input Timing
21.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
21.4 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
21.5 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or
medium-speed clocks (φ/2, φ/4, φ/8, φ/16, φ/32).