Datasheet

Section 21 Clock Pulse Generator
REJ09B0140-0900 Rev. 9.00 Page 673 of 846
Sep 16, 2010
H8S/2215 Group
EXTAL
XTAL
EXTAL
XTAL
External clock input
Open
External clock input
(a) XTAL pin left open
(b) Complementary clock input at XTAL pin
Figure 21.5 External Clock Input (Examples)
Table 21.4 shows the input conditions for the external clock.
Table 21.4 External Clock Input Conditions
VCC
= 2.7 V to 3.6 V
VCC
= 3.0 V to 3.6 V*
Test
Item Symbol
Min Max Min Max Unit Conditions
External clock input low
pulse width
t
EXL
25 — 15.5 — ns
External clock input high
pulse width
t
EXH
25 — 15.5 — ns
External clock rise time t
EXr
— 6.25 — 5.25 ns
External clock fall time t
EXf
— 6.25 — 5.25 ns
Figure 21.6
Clock low pulse width
level
t
CL
0.4 0.6 0.4 0.6 t
cyc
Figure 24.3
Clock high pulse width
level
t
CH
0.4 0.6 0.4 0.6 t
cyc
Note: * Available only in H8S/2215R, H8S/2215T and H8S/2215C.
The external clock input conditions when the duty adjustment circuit is not used are shown in
table 21.5. When the duty adjustment circuit is not used, note that the maximum operating
frequency depends on the external clock input waveform. For example, if t
EXL
= T
EXH
= 31.25 ns