Datasheet

Section 21 Clock Pulse Generator
REJ09B0140-0900 Rev. 9.00 Page 669 of 846
Sep 16, 2010
H8S/2215 Group
Bit Bit Name Initial Value R/W Description
7 PSTOP 0 R/W φ Clock Output Disable
Controls φ output.
Operation differs depending on the mode. For details, see
section 22.7, φ Clock Output Disabling Function.
0: φ output, fixed high, or high impedance
1: Fixed high or high impedance
6 — 0 R/W Reserved
This bit can be read from or written to, but the write value
should always 0.
5, 4 — All 0 — Reserved
These bits are always read as 0.
3 — 0 R/W Reserved
This bit can be read from or written to, but the write value
should always be 0.
2
1
0
SCK2
SCK1
SCK0
0
0
0
R/W
R/W
R/W
System Clock Select 2 to 0
These bits select the bus master clock.
000: High-speed mode
001: Medium-speed clock is φ/2
010: Medium-speed clock is φ/4
011: Medium-speed clock is φ/8
100: Medium-speed clock is φ/16
101: Medium-speed clock is φ/32
11×: Setting prohibited
Legend:
×: Don’t care