Datasheet

Section 21 Clock Pulse Generator
REJ09B0140-0900 Rev. 9.00 Page 667 of 846
Sep 16, 2010
H8S/2215 Group
Section 21 Clock Pulse Generator
This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master
clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, duty
adjustment circuit, medium-speed clock divider, bus master clock selection circuit, USB operating
clock oscillator, PLL (Phase Locked Loop) circuit, and USB operating clock selection circuit. A
block diagram of clock pulse generator is shown in figure 21.1.
EXTAL
XTAL
Duty
adjustment
circuit
EXTAL
XTAL
System
clock
oscillator
USB
operation
clock
selection
circuit
EXTAL
XTAL
EXTAL48
XTAL48
USB
operation
clock
oscillator
Medium-
speed
clock divider
System clock
to φ pin
USB operation
clock
to USB
USB clock
to USB
Internal clock
to peripheral
modules
Bus master cloc
k
To CPU,
DTC,
DMAC,
φ/2
to φ/32
SCK2 to SCK0
UCKS3 to UCKS0
SCKCR
RFCUT
48 MHz
LPWRCR
UCTLR
Bus
master
clock
selection
circuit
φ
Legend:
LPWRCR: Low power control register
SCKCR: System clock control register
UCTLR: USB control register
Note: * × 2 is available only in H8S/2215R and H8S/2215T.
PLL circuit
(× 3 or × 2
∗
)
Figure 21.1 Block Diagram of Clock Pulse Generator
CPG0600A_000120020100