Datasheet

Section 19 Flash Memory (F-ZTAT Version)
REJ09B0140-0900 Rev. 9.00 Page 655 of 846
Sep 16, 2010
H8S/2215 Group
Start
Set EBR1 (2)
Enable WDT
Disable WDT
Read verify data
Increment address
Verify data = all 1s?
Last address of block?
All erase block erased?
Set block start address as verify address
H'FF dummy write to verify address
Set SWE1 bit in FLMCR1
n = 1
Set ESU1 bit in FLMCR1
Set E1 bit in FLMCR1
Wait (x) μs
Wait (y) μs
Clear E1 bit in FLMCR1
Clear EV1 bit in FLMCR1
Wait (z) μs
Clear ESU1 bit in FLMCR1
Wait (a) μs
Wait (b) μs
Wait (g) μs
Clear EV1 bit in FLMCR1
n ← n + 1
Wait (h) μs
Clear SWE1 bit in FLMCR1
Wait (q) μs
Clear EV1 bit in FLMCR1
n ≥ (N)?
Wait (h) μs
Clear SWE1 bit in FLMCR1
Wait (q) μs
Erase failure
End of erasing
Wait (e) μs
No
No
Ye s
Ye s
No
No
Ye s
Ye s
*
1
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
5
*
2
*
2
*
2
*
2
*
3
*
4
Notes: 1. Pre-write (clearing data in the block to be erased to 0) is not required.
2. x, y, z, a, b, g, e, h, q, and N are shown in section 24.8, Flash Memory Characteristics.
3. Veryfy data is read in 16 bits.
4. Only 1 bit in the EBR register must be set. Two or more bits in EBR cannot be set.
5. Erasure is performed in block units. To erase multiple blocks, each block must be erased sequentially.
Figure 19.12 Erase/Erase-Verify Flowchart