Datasheet

Section 19 Flash Memory (F-ZTAT Version)
REJ09B0140-0900 Rev. 9.00 Page 653 of 846
Sep 16, 2010
H8S/2215 Group
Write pulse application subroutine
Subroutine Write Pulse
End Sub
Set PSU1 bit in FLMCR1
WDT enable
Disable WDT
Note: 7. Write Pulse Width
Wait (y) µs
Set P1 bit in FLMCR1
Wait (z0), (z1), or (z2)
µs
Clear P1 bit in FLMCR1
Wait (α)
µs
Clear PSU1 bit in FLMCR1
Wait (β)
µs
Start of programming
End of programming
*
5
*
6
*
6
*
6
*
6
*
6
*
6
*
6
*
6
*
6
Original Data
(D)
Verify Data
(V)
Reprogram Data
(X)
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Reprogram Data Computation Table
1
0
1
1
0
1
0
1
0
0
1
1
Reprogram Data
(X')
Verify Data
(V)
Additional-
Programming Data (Y)
Comments
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
Additional programming not to be executed
Additional-Programming Data Computation Table
0
1
1
1
0
1
0
1
0
0
1
1
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address
written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes;
in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below
(comparison between the data stored in the program data area and the verify data).
Bits for which the reprogram data is 0 are programmed in the next reprogramming loop.
Therefore, even bits for which programming has been completed will be subjected
to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data,
and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of z0 or z1 is applied according to the progress of the programming operation. See note 7 for details of the pulse widths.
When writing of additional-programming data is executed, a z2 write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
6. x, y, z0, z1, z2, α, β, γ, ε, η, θ, N1, and N2 are shown in section 24.8, Flash Memory Characteristics.
START
End of programming
Set SWE1 bit in FLMCR1
Start of programming
Wait (x)
µs
n = 1
m = 0
No
No No
Yes
Yes
Yes
Wait (γ) µs
Wait (ε) µs
*
2
*
4
*
1
Wait (η) µs
Apply Write pulse Z0 µs or Z1 µs
Sub-Routine-Call
Set PV1 bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Write data =
verify data?
*
4
*
3
*
1
Transfer reprogram data to reprogram data area
Reprogram data computation
*
4
Transfer additional-programming data to
additional-programming data area
Additional-programming data computation
Clear PV1 bit in FLMCR1
Clear SWE1 bit in FLMCR1
m = 1
Reprogram
See Note 7 for pulse width
m = 0 ?
Increment address
Programming failure
Yes
Clear SWE1 bit in FLMCR1
Wait (θ) µs
No
Yes
N1 ≥ n?
No
Yes
N1 ≥ n ?
Wait (θ)
µs
n ≥ (N1 + N2)?
n ← n + 1
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Store 128-byte program data in program
data area and reprogram data area
Apply Write Pulse (Additional programming) z2 µs
Sub-Routine-Call
128-byte
data verification completed?
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
P1 bit set time (µs)
1z2
2
N1-1
N1
N1+1
N1+2
N1+3
N1+N2-1
N1+N2-2
N1+N2
z2
z2
z2
⎯
⎯
⎯
⎯
⎯
⎯
z0
z0
z0
z0
z1
z1
z1
z1
z1
z1
Number of Writes n
Program
Re -program
*
6
*
6
*
6
*
6
*
6
*
6
Figure 19.11 Program/Program-Verify Flowchart