Datasheet

Section 19 Flash Memory (F-ZTAT Version)
Page 644 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
Table 19.4 SCI Boot Mode Operation
Item Host Operation LSI Operation
Branches to boot program at reset-
start.
Continuously transmits data H'00
at specified bit rate.
Measures low-level period of
receive data H'00.
Calculates bit rate and sets it in
BRR of SCI_2.
Bit rate adjustment
Transmits data H'55 when data
H'00 is received error-free.
Transmits data H'00 to host as
adjustment end indication.
Transmits data H'AA to host when
data H'55 is received.
Transmits number of
bytes (N) of programming
control program
Transmits number of bytes (N) of
programming control program to
be transferred as 2-byte data (low-
order byte following high-order
byte)
Echobacks the 2-byte data received
as verification data.
Transmits 1-byte of
programming control
program (repeated for N
times)
Transmits 1-byte of programming
control program
Echobacks received data to host
and also transfers it to RAM
Flash memory erase Checks flash memory data, erases
all flash memory blocks in case of
written data existing, and transmits
data H'AA to host. (If erase could
not be done, transmits data H'FF to
host and aborts operation.)
Programming control
program execution
Branches to programming control
program transferred to on-chip
RAM and starts execution.
Table 19.5 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is
Possible
Host Bit Rate System Clock Frequency Range of LSI
19,200 bps HD64F2215: 13 to 16 MHz
9,600 bps HD64F2215R: 13 to 24 MHz
4,800 bps HD64F2215T: 16 MHz and 24 MHz