Datasheet

Section 15 Universal Serial Bus Interface (USB)
Page 592 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
15.9.4 FIFO Clear
If the USB cable is disconnected during communication, old data may be contained in the FIFO.
Accordingly, FIFO must be cleared immediately after USB cable connection. In addition, after bus
reset, all FIFO must also be cleared. Note, however, that FIFOs that are currently used for data
transfer to or from the host must not be cleared.
15.9.5 IRQ6 Interrupt
A suspend/resume interrupt requested by IRQ6 must be specified as falling-edge sensitive.
15.9.6 Data Register Overread or Overwrite
When the CPU reads or writes to data registers, the following must be noted:
• Transmit data registers (UEDR0i, UEDR1i, UEDR2i, UEDR3i, UEDR4i, UEDR5i)
Data to be written to the transmit data registers must be within the maximum packet size. For
the transmit data registers of EP2i, EP3i, and EP4i having a dual-FIFO configuration, data to
be written at any time must be within the maximum packet size. In this case, after a data write,
the FIFO is switched to the other FIFO, enabling an further data write when the PKTE bit of
UTRG is set to 1 (in EP3i, the same operation is automatically performed when the SOF
packet is received). Accordingly, data of size corresponding to two FIFO must not be written
to the transmit data registers of EP2i, EP3i, and EP4i at a time.
• Receive data registers (UEDR0o, UEDR2o, UEDR3o, UEDR4o)
Receive data registers must not read a data size that is greater than the effective size of the read
data item. In other words, receive data registers must not read data with data size larger than
that specified by the receive data size register. For the receive data registers of EP2o, EP3o,
and EP4o having a dual-FIFO configuration, data to be read at any time must be within the
maximum packet size. In this case, after reading the currently selected FIFO, set the RDFN bit
of UTRG to 1 (in EP3o, the same operation is automatically performed when the SOF packet
is received). This switches the FIFO to the other FIFO and updates the receive data size,
enabling the next data read. In addition, if there is no receive data in a FIFO, data must not be
read. Otherwise, the pointer that controls the internal module FIFO is updated and correct
operation cannot be guaranteed.