Datasheet

Section 15 Universal Serial Bus Interface (USB)
REJ09B0140-0900 Rev. 9.00 Page 591 of 846
Sep 16, 2010
H8S/2215 Group
15.9 Usage Notes
15.9.1 Operating Frequency
• In H8S/2215
When the on-chip PLL circuit is used, the system clock of this LSI must be 16 MHz. This 16-
MHz system clock, used as base clock, is tripled in the on-chip PLL circuit to generate the 48-
MHz USB operating clock. When the USB operating clock (48 MHz) oscillator or 48-MHz
external clock is used, the system clock of the LSI must be 13-MHz to 16-MHz. Medium-
speed mode is not supported; use full-speed mode.
• In H8S/2215R, H8S/2215T and H8S/2215C
When the on-chip PLL circuit is used, the system clock of this LSI must be 16 MHz or 24
MHz. If the system clock frequency is 16 MHz, it is tripled by the on-chip PLL circuit, and if
the system clock frequency is 25 MHz, it is doubled, to generate the 48-MHz USB operating
clock. When the USB operating clock (48 MHz) oscillator or 48-MHz external clock is used,
the system clock of the LSI must be 13 MHz to 24 MHz*. Medium-speed mode is not
supported; use full-speed mode.
Note: * On the H8S/2215T, use a 16-MHz or 24-MHz system clock for the MCU, even if a 48-
MHz oscillator or 48-MHz external clock is used as the USB operation clock. For the
H8S/2215C, use a MCU system clock in the range of 16 MHz to 24 MHz.
15.9.2 Bus Interface
This module’s interface is based on the bus specifications of external area 6. Before accessing the
USB, area 6 must be specified as having an 8-bit bus width and 3-state access using the bus
controller register. In mode 7 (single-chip mode), the USB module cannot be accessed. In mode 6
(internal ROM enabled mode), CS6 and A7 to A0 pins are used as inputs at initialization and USB
cannot be accessed. Before access to this module, set P72DDR to 1 and PC7DDR to PC0DDR to
H'FF, respectively, to use CS6 and A7 to A0 pins as outputs. In mode 4 or 5 (on-chip ROM
disabled mode), set P72DDR to 1 to use the CS6 pin as an output.
15.9.3 Setup Data Reception
The following must be noted for the EP0s FIFO used to receive 8-byte setup data. The USB is
designed to always receive setup commands. Accordingly, write from the UDC has higher priority
than read from the LSI. If the reception of the next setup command starts while the is LSI reading
data after completing reception, this data read from the LSI is forcibly cancelled and the next setup
command write starts. After the next setup command write, data read from the LSI is thus
undefined. Read operation is forcibly disabled because data cannot be guaranteed if DP-RAM
used as FIFO accesses the same address for write and read.