Datasheet

Section 15 Universal Serial Bus Interface (USB)
REJ09B0140-0900 Rev. 9.00 Page 543 of 846
Sep 16, 2010
H8S/2215 Group
15.3.49 USB Test Registers 2 and A to F (UTSTR2, UTSRA to UTSRF)
UTSTR2 and UTSRTA to UTSRTF are test registers and cannot be written to.
15.3.50 Module Stop Control Register B (MSTPCRB)
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
MSTPB7
MSTPB6
MSTPB5
MSTPB4
MSTPB3
MSTPB2
MSTPB1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Module Stop Bits
For details, refer to section 22.1.2, Module Stop
Control Registers A to C (MSTPCRA to MSTPCRC).
0 MSTPB0 1 R/W
Module Stop USB
0: Cancels USB module stop mode. A clock is provided
for the USB module. After this bit has been cleared,
the USB operating clock (48 MHz) oscillator or
internal PLL circuit starts operation. Registers in the
USB module must be accessed after the USB
operating clock stabilization time (CK48READY bit of
UIFR3 is set ) has passed.
1: Places the USB module in stop mode. Both the USB
operating clock (48 MHz) oscillator and internal PLL
circuit stop operation. In this mode, the USB module
register contents are maintained.
Note: For details on USB module stop mode cancellation procedure, refer to section 15.5,
Communication Operation.
15.4 Interrupt Sources
This module has three interrupt signals. Table 15.5 shows the interrupt sources and their
corresponding interrupt request signals. EXIRQ interrupt signals are activated at low level. The
EXIRQ interrupt requests can only be detected at low level (specified as level sensitive). The
suspend/resume interrupt request IRQ6 must be specified to be detected at the falling edge
(falling-edge sensitive) by the interrupt controller register.