Datasheet

Section 15 Universal Serial Bus Interface (USB)
Page 536 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
15.3.44 USB Data Status Register (UDSR)
UDSR indicates whether the IN FIFO data registers (EP0i, EP1i, EP2i, EP4i, and EP5i) contain
valid data or not. A bit in USDR is set when data written to the corresponding IN FIFO becomes
valid after the corresponding PKTE bit in UTRG is set to 1. A bit in USDR is cleared when all
valid data is sent to the host. For EP2i and EP4i, having a dual-FIFO configuration, the
corresponding bit in USDR is cleared to 0 and FIFO becomes empty.
Bit Bit Name Initial Value R/W Description
7, 6 — All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
5 EP5iDE 0 R EP5i Data Enable
0: Indicates that the EP5i contains no valid data
1: Indicates that the EP5i contains valid data
4 EP4iDE 0 R EP4i Data Enable
0: Indicates that the EP4i contains no valid data
1: Indicates that the EP4i contains valid data
3 — 0 R Reserved
This bit is always read as 0 and cannot be modified.
2 EP2iDE 0 R EP2i Data Enable
0: Indicates that the EP2i contains no valid data
1: Indicates that the EP2i contains valid data
1 EP1iDE 0 R EP1i Data Enable
0: Indicates that the EP1i contains no valid data
1: Indicates that the EP1i contains valid data
0 EP0iDE 0 R EP0i Data Enable
0: Indicates that the EP0i contains no valid data
1: Indicates that the EP0i contains valid data